The present invention relates to a resistance change nonvolatile memory device, a semiconductor device, and a method of manufacturing a resistance change nonvolatile memory device.
In nonvolatile memory fields, there has been much research on flash memories, ferroelectric memories (Ferroelectric Random Access Memory: FeRAM), magnetic memories (Magnetic Random Access Memory: MRAM), OUM (Ovonic Unified Memory) and the like. As nonvolatile memories different from these related-art ones, however, resistance change memories (Resistance Random Access Memory: ReRAM) have recently been proposed. For example, the resistance change memory described in Non-patent Document 1 can write data by setting the resistance of the resistance change layer of a memory cell by application of a voltage pulse. In addition, it can read data by measuring resistance in a non-destructive manner. This resistance change memory can be multivalued because memory cells have a small area. Therefore, it has a possibility exceeding the existing nonvolatile memories. In Non-patent Document 1, PCMO (Pr0.7Ca0.3MNO3) and YBCC (YBa2Cu3Oy) are used as the resistance change layer. Another proposal has been made for a resistance change memory. For example, the resistance change memory described in Non-patent Document 2 uses a polycrystalline NiOx (x=from 1 to 1.5) film of about 50 nm thick as the resistance change layer. Switching to a low resistance state or to a high resistance state is achieved by applying a positive voltage to the upper electrode. The resistance change memory described in Non-patent Document 3 uses a microcrystalline TiO2 film of 80 nm thick as the resistance change layer.
In general, a memory cell of a resistance change memory is equipped with a control transistor and a resistance change element. The resistance change memory having such a memory cell is also called “1T1R type”. FIG. 1 is a plan view showing the configuration of a related-art 1T1R type resistance change memory. A 1T1R type resistance change memory 190 is equipped with a plurality of word lines (or gates) 122, a plurality of bit lines (or second wirings) 106, a plurality of common lines 108, and a plurality of memory cells MC. The word lines (or gates) 122 extend in the direction Y. The bit lines (or second wirings) 106 extend in the direction X. The common lines 108 extend in the direction Y. The memory cells MC are provided, respectively, at positions corresponding to the intersections between the word lines 122 and the bit lines 106.
FIG. 2 is a cross-sectional view showing the configuration of the a-a′ cross-section in FIG. 1. It shows the configuration of one memory cell MC. The memory cell MC is equipped with a control transistor 102 and a resistance change element 101. A semiconductor substrate 170 has thereon an element isolation region 171 and a control transistor 102. The control transistor 102 is equipped with a gate insulating film 123, a gate 122 (word line), a drain 121, a source 124, and a sidewall 125. Contacts 104 are coupled to the drain 121 and the source 124, respectively. The control transistor 102 and the contacts 104 are covered with a first interlayer insulating film 151 and a first cap insulating film 161. The contact 104 on the side of the drain 121 is coupled to a first wiring 103 composed of a barrier metal 132 and a copper (Cu) 131 via an opening portion of the first cap insulating film 161. The first wiring 103 is covered with a second interlayer insulating film 152 and a second cap insulating film 162. The resistance change element 101 of the resistance change memory is coupled to the first wiring 103 via an opening portion of the second cap insulating film 162. The resistance change element 101 has an MIM (Metal/Insulator/Metal) structure composed of a lower electrode 113 to be coupled to the first wiring 103, a resistance change layer 112 on the lower electrode 113, and an upper electrode 111 on the resistance change layer 112. The upper electrode 111 is coupled to a first via 105 composed of a barrier metal 135 and copper (Cu) 134 and the second wiring 106 (bit line). The contact 104 on the side of the source 124 is coupled to the common line 108 via an opening portion of the first cap insulating film 161. The resistance change element 101 is covered with a third interlayer insulating film 153 and a third cap insulating film 163. The second wiring 106 is provided on the third cap insulating film 163. As shown in FIG. 2, in the related-art structure, the resistance change element 101 is formed between wiring layers (here, between the wiring layer of the first wiring 103 and the wiring layer of the second wiring 106). In this case, the resistance change element 101 has an MIM capacitor structure isolated from the resistance change element 101 of an adjacent memory cell MC. The resistance change element 101 can be considered to have a (parasitic) capacitance.
A method of operating the related-art structure will next be described. First, initialization is conducted in the following manner. A positive voltage is applied to the upper electrode 111 via the second wiring 106 to reduce the resistance of the resistance change layer 112 (Forming). At this time, the voltage to be applied to the gate 122 is adjusted so as to impose a current limitation by a saturated current value of the control transistor 102. As a result, the resistance change layer 112 has a desired resistance value. Incidentally, Forming may be conducted by applying a positive voltage to the lower electrode 113 instead of applying it to the upper electrode 111.
Write operation is conducted in the following manner. For switching from a low resistance state to a high resistance state, a positive voltage is applied to the source 124 and the gate 122. For switching from a high resistance state to a low resistance state, a positive voltage is applied to the upper electrode 111 and the gate 122. At this time, a voltage higher than that applied upon switching to a high resistance state is applied to the common line 108. In addition, a voltage to be applied to the gate 122 is adjusted so as to impose a current limitation by a saturated current value of the control transistor 102. As a result, the resistance change layer 112 has a desired resistance value. Switching operation from a high resistance state to a low resistance state or switching operation from a low resistance state to a high resistance state can also be made by applying a positive voltage to the upper electrode 111 instead of the source 124.
As a related technology, Japanese Patent Laid-Open No. 2009-117668 discloses a variable resistor for nonvolatile memory, a manufacturing method thereof, and a nonvolatile memory. A variable resistor for nonvolatile memory according to this document is equipped with an interlayer insulating film, a lower electrode, a variable resistance layer, an upper electrode, and a second-level wiring layer. The interlayer insulating film is provided on the first-level wiring layer and has a through-hole to be coupled to the first-level wiring layer. The lower electrode is provided in the through-hole and coupled to the first-level wiring layer. The variable resistance layer is provided on the lower electrode in the through-hole. The upper electrode is provided on the variable resistance layer in the through-hole. The second-level wiring layer is provided on the interlayer insulating film and coupled to the upper electrode. Another variable resistor for nonvolatile memory according to this document is equipped with a variable resistance layer, an interlayer insulating film, and a plug metal. The variable resistance layer is provided on the surface of the first-level wiring layer. The interlayer insulating film is provided on the first-level wiring layer. The plug metal is provided in the interlayer insulating film and coupled to the variable resistance layer.
Japanese Patent Laid-Open No. 2010-027753 discloses a nonvolatile memory element and a manufacturing method thereof. This nonvolatile memory element is equipped with a first electrode, an interlayer insulating film, an opening portion, a resistance change film, and a second electrode. The first electrode is formed on a substrate. The interlayer insulating film is formed on the first electrode. The opening portion penetrates through the interlayer insulating film. The resistance change film is formed at least on the bottom portion of the opening portion and coupled to the first electrode. The second electrode is formed adjacent to the resistance change film and at the same time, buried in the opening portion. The resistance change film interposed between the first electrode and the second electrode configures a memory portion characterized in that it undergoes an increase or decrease in resistance by application of an electric pulse. Data is stored or read, depending on a change in the resistance value. This means that the first electrode also serves as a first wiring. An opening portion is formed on the first electrode. The opening portion has, on the bottom portion and inner wall thereof, the resistance change layer. The second electrode is formed on the inner side of the resistance change layer.
Japanese Patent Laid-Open No. 2009-295842 discloses a semiconductor memory device and a manufacturing method thereof. This semiconductor memory device is equipped with an interlayer insulating film, a conductive pattern, a lower electrode, a transition metal oxide film, and an upper electrode. The interlayer insulating film is formed above the substrate and has a trench. The conductive pattern is buried in the interlayer insulating film surrounded with a trench. The lower electrode is formed at least on the conductive pattern and the side wall of the trench. The transition metal oxide film is formed on the lower electrode. The upper electrode is formed on the transition metal oxide film on at least a portion of the conductive pattern and the side wall of the trench.
Japanese Patent Laid-Open No. 2006-128680 discloses selective formation of a metal layer in an integrated circuit. This method for selectively forming a conductive layer in an integrated circuit includes a step of providing a first surface composed of copper and a second surface and a step of bringing the first surface and the second surface into contact with a gas phase compound of a noble metal to electively form the conductive layer made of the noble metal on the first surface compared with the second surface.    [Patent Document 1]
Japanese Patent Laid-Open No. 2009-117668    [Patent Document 2]
Japanese Patent Laid-Open No. 2010-027753    [Patent Document 3]
Japanese Patent Laid-Open No. 2009-295842    [Patent Document 4]
Japanese Patent Laid-Open No. 2006-128680    [Non-patent Document 1]
W. W. Zhuang et al., “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM, Article No. 7.5, pp.193-196, 2002.    [Non-patent Document 2]
G.-S. Park et al., “Observation of electric-field induced Ni filament channels in polycrystalline NiOx film”, APL, Vol. 91, pp. 222103, 2007.    [Non-patent Document 3]
C. Yoshida et al., “High speed resistive switching in Pt/TiO2/TiN film for nonvolatile memory application”, APL, Vol. 91, pp. 223510, 2007.    [Non-patent Document 4]
J. F. Gibbons et al., “Switching properties of thin NiO Films”, Solid State Electronics, vol. 7, pp.785, 1964.    [Non-patent Document 5]
K. Kinoshita et al., “Bias polarity dependent data retention of resistive random access memory consisting of binary transition metal oxide”, APL, vol. 89, pp. 103509, 2006.